View HT16K23_9006343.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

rev. 1.10 1 july 01, 2011 rev. 1.00 pb july 01, 2011 HT16K23 ram mapping 20*4/16*8 lcd controller driver with keyscan feature logic voltage: 2.4~5.5v integrated rc oscillator various display mode s C max. 20*4 patterns, 20 segments, 4 commons, 1/3 bias, 1/4 duty C max. 16*8 patterns, 16 segments, 8 commons, 1/4 bias, 1/8 duty i 2 c-bus interface key scan function C max. 20*1 matrix key scanning in 20*4 display mode C max. 16*1 matrix key scanning in 16*8 display mode 16*8 bits ram for display data storage selectable hardware interrupt r/w address auto increment manufactured in silicon gate coms process 28-pin sop package applications industrial control indicator digital clock, thermometer, counter, voltmeter combo set. vcr set instrumentation readouts other consumer application lcd displays general description the HT16K23 is a memory mapping and multi- function lcd controller driver. the max. display segment numbers in the device are 80 patterns (20 segments and 4 commons) or 128 patterns (16 segments and 8 commons). the max. key scan circuits are 20*1 matrix or 16*1 matrix. the software configuration feature of the HT16K23 makes it suitable for multiple lcd applications including lcd modules and display subsystems. the HT16K23 supports a hardware interrupt using register setting. the HT16K23 is compatible with most microcontrollers and communicates via a two-line bidirectional i 2 c-bus.
rev. 1.10 2 july 01, 2011 HT16K23 block diagram lcd driver / keyscan circuit / device address selecting circuit display ram 16*8bits timing generator i 2 c controller vdd vss sda scl power_on reset seg0/k0 key data ram 20*1 bits seg1/k1 seg2/k2 seg15/k15/int seg14/k14 seg13/k13 lcd bias circuit internal rc oscillator com3 com2 com1 com0 seg19/com4/k19/int seg18/com5/k18 seg17/com6/k17 seg16/com7/k16 pin assignment

rev. 1.10 3 july 01, 2011 HT16K23 pad coordinates unit: m 2 no pad name x y no pad name x y 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 com3 seg19/com4/k19/int seg18/com5/k18 seg17/com6/k17 seg16/com7/k16 seg15/k15/int n.c. seg14/k14 seg13/k13 seg12/k12 seg11/k11 seg10/k10 seg9/k9 seg8/k8 seg7/k7 -400.967 -479.400 -479.400 -479.400 -479.400 -479.400 -182.270 -3.500 81.500 166.500 251.500 336.500 421.500 479.400 479.400 924.900 -496.281 -592.981 -677.981 -762.981 -868.000 -392.291 -924.900 -924.900 -924.900 -924.900 -924.900 -924.900 -538.200 -453.200 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 seg6/k6 seg5/k5 seg4/k4 seg3/k3 seg2/k2 seg1/k1 seg0/k0 scl sda vlcd vdd vss com0 com1 com2 479.400 479.400 479.400 479.400 479.400 479.400 400.967 305.917 220.917 132.317 47.317 -60.967 -145.967 -230.967 -315.967 -368.200 -283.200 -198.200 -113.200 -28.200 56.800 924.900 924.900 924.900 924.900 924.950 924.950 924.900 924.900 924.900 pad assignment 14 30 29 2 4 7 (0, 0) 3 5 6 8 9 10 11 12 13 15 16 17 18 19 20 21 22 23 24 25 26 27 28 1 seg0/k0 scl sda vlcd vdd vss com0 com1 com2 com3 seg19/com4/k19/int seg18/com5/k18 seg17/com6/k17 seg16/com7/k16 seg15/k15/int seg9/k9 seg10/k10 seg11/k11 seg12/k12 seg13/k13 seg14/k14 seg1/k1 seg2/k2 seg3/k3 seg4/k4 seg5/k5 seg6/k6 seg7/k7 seg8/k8 n . c . chip size: 1167 2058m 2 the ic substrate should be connected to vss in the pcb layout artwork. the vlcd and vdd should be bonded together.
rev. 1.10 4 july 01, 2011 HT16K23 pin description pin name type description sda i/o serial data input/output for i 2 c interface. scl i serial clock input for i 2 c. v dd positive power supply for logic circuits. v ss negative power supply for logic circuits, ground. com0 ~ com3 o lcd common output. seg0/k0 ~ seg14/k14 i/o lcd segment output. key data input, internal pull-low during key scan. seg15/k15/int i/o when the m bit of the mode set command is set to 1, and the int/row bit of the mode set command is set to 0, this pin becomes an lcd segment output and key data input with internal pull-low during key scan. when the m bit of the mode set command is set to 1, and the int/row bit of the mode set command is set to 1, this pin becomes an int pin, interrupt signal out. int is output active-low when the act bit of mode set command is set to 0, the int output is active-high when the act bit of the mode set command is set to 1 seg16/com7/k16 ~ seg18/com5/k18 i/o when the m bit of the mode set command is set to 0, this pin becomes an lcd segment output and a key data input with internal pull-low during a key scan. when the m bit of the mode set command is set to 1, this pin becomes an lcd common output. seg19/com4/k19/int i/o when the m bit of the mode set command is set to 0, and the int/row bit of the mode set command is set to 0, this pin becomes a lcd segment output and a key data input with internal pull-low during key scan. when the m bit of the mode set command is set to 0, and the int/row bit of the mode set command is set to 1, this pin becomes an int pin, interrupt signal out. the int output is active- low when the act bit of the mode set command is set to 0, the int output active-high when the act bit of the mode set command is set to 1 when the m bit of the mode set command is set to 1, this pin becomes an lcd common output.
rev. 1.10 5 july 01, 2011 HT16K23 approximate internal connections vdd gnd scl , sda vselect - on vselect - off com0 ~ com3 vselect - on vselect - off seg 15 / k15 /int seg 19 /com 4 /k 19 / int vselect - on vselect - off seg0/k 0 ~ seg 14 /k14 seg 16 / com7 /k 16 ~ seg 18 / com5 /k 18 absolute maximum ratings supply voltage ....................................................................................................................... v ss -0.3v to v ss +6.5v input voltage ......................................................................................................................... v ss -0.3v to v dd +0.3v storage temperature ........................................................................................................................ -55 c to 150c operating temperature ...................................................................................................................... -40 c to 85 c note: these are stress ratings only. stresses exceeding the range specifed under absolute maximum ratings may cause substantial damage to the device. functional operation of this device at other conditions beyond those listed in the specifcation is not implied and prolonged exposure to extreme conditions may affect device reliability.
rev. 1.10 6 july 01, 2011 HT16K23 d.c. characteristics v dd =2.4~5.5v; ta=25c (unless otherwise specifed) symbol parameter test condition min. typ. max. unit v dd condition v dd operating voltage 2.4 5.5 v i dd 1 operating current 3v no load, lcd on , 20*4 display mode 155 310 a 5v 260 420 a i dd 2 operating current 3v no load, lcd off , 20*4 display mode 8 30 a 5v 20 60 a i stb standby current 3v no load, standby mode 1 3 a 5v 2 5 a v il input low voltage sda, scl 0 0.3v dd v v i h input high voltage sda, scl 0. 7 v dd v dd v i il input leakage current v in = v ss or v dd -1 1 a i ol low level output current 3v v ol =0.4v, sda 3 ma 5v 6 ma i ol1 lcd common sink current 3v v ol =0.3v 80 160 a 5v v ol =0.5v 180 360 a i oh1 lcd common source current 3v v oh =2.7v -80 -120 a 5v v oh =4.5v -120 -200 a i ol2 lcd segment sink current 3v v ol =0.3v 60 120 a 5v v ol =0.5v 120 200 a i oh2 lcd segment source current 3v v oh =2.7v -40 -70 a 5v v oh =4.5v -70 -140 a i ol 3 int sink current 3v v ol =0.3v 1 ma 5v v ol =0.5v 2 ma i oh 3 int source current 3v v oh =2.7v -1 ma 5v v oh =4.5v -2 ma r pl input pull-low resistance 3v seg0/k0~seg19/k19, during keyscan period 220 400 600 k 5v 220 400 600
rev. 1.10 7 july 01, 2011 HT16K23 a.c. characteristics v dd =2.4~5.5v; ta=25c (unless otherwise specifed) symbol parameter test condition min. typ. max. unit v dd condition f lcd lcd frame frequency 3v 20*4 display mode 16*8 display mode 58 72 90 hz 5v t off v dd off times v dd drop down to 0v 20 ms t sr v dd slew rate 0.05 v/ms note: 1. if the power on reset timing conditions are not satisfed in the power on/off sequence, the internal power on reset circuit will not operate normally. 2. if vdd drops below the minimum voltage of the operating voltage spec. during operating, the power on reset timing conditions must also be satisfed. that is, vdd must drop to 0v and remain at 0v for 20ms (min.) before rising to the normal operating voltage. a.c. characteristics i 2 c-bus ta=25c (unless otherwise specifed) symbol parameter test condition v dd =2.4v to 5.5v v dd =3.0v to 5.5v unit condition min. max. min. max. f scl clock frequency 100 400 khz t buf bus free time time in which the bus must be free before a new transmission can start 4.7 1.3 s t hd; sta start condition hold time after this period, the frst clock pulse is generated 4 0.6 s t low scl low time 4.7 1.3 s t high scl high time 4 0.6 s t su; sta start condition set-up time only relevant for repeated start condition. 4.7 0.6 s t hd; dat data hold time 0 0 s t su; dat data set-up time 250 100 ns t r rise time note 1 0.3 s t f fall time note 0.3 0.3 s t su; sto stop condition set-up time 4 0.6 s t aa output valid from clock 3.5 0.9 s t sp input filter time constant (sda and scl pins) noise suppression time 100 50 ns note: these parameters are periodically sampled but not 100% tested.
rev. 1.10 8 july 01, 2011 HT16K23 timing diagrams i 2 c timing sda scl t f t hd:sda t low t r t hd:dat t su:dat t high t su:sta t hd:sta s sr t sp t su:sto p t buf s t aa sda out power-on reset timing functional description power-on reset when power is turned on, the ic is initialised by the internal power-on reset circuit. the status of the internal circuit after initialization is as follows: display mode is 20*4, 20 segments and 4 commons. system oscillator is off. lcd display is off. key scan stopped. all common pins are set to vss. all segment pins are in an input state. seg19/com4/int pin is set to segment driver. the control registers, key data ram and display data ram are set to a default value. data transfers on the i 2 c-bus should be avoided for 1 ms following power-on to allow completion of the reset procedure.
rev. 1.10 9 july 01, 2011 HT16K23 standby mode in the standby mode, the HT16K23 cannot accept any input command or write data to the display ram except for the system set command. if standby mode is selected with the s bit of system set command is set to 0, the status of the standby mode is as follows: system oscillator is off. lcd display is off. key scan stopped. all key data and int fags are cleared, until the standby mode is cancelled. the key matrix is pushed by any key or if the s bit of the system set command is set to 1, this standby mode will be cancelled and the device will wake-up. all common pins are set to vss. if the int/row bit of mode set command is set to 0, all segment pins are changed to input pins. if the int/row bit of mode set command is set to 1: all segment pins are changed to input pins except for the int pin (output). the int pin output keeps a high level when the act bit of the mode set command is set to 0,.the int pin output keeps to a low level when the act bit of the mode set command is set to 1, if the int/row bit of mode set command is set to 1. wake-up wake-up is implemented by a key press by any key or if the s bit of the system set command is set to 1. then a key scan is performed. system oscillator restarts for normal operation. the previous output will be displayed until updated by each mode command set. the relationship between wake-up and any key press delay timeless and int output and int fag status is as follows: wake-up standby mode command set from mcu read key data command set from mcu int flag or int pin output any key press release key 2 frame cycle normal active status HT16K23 operation status standby status press 2 frame cycle < 2 frame cycle release key normal active status press release (when the act bit is set to 1) key data are updated key data are updated when after the key data has been read,clears the key data ram. when after the key data has been read,clears the key data ram.
rev. 1.10 10 july 01, 2011 HT16K23 system set command this command is used to set the follow functions. the HT16K23 operates in normal mode or standby mode. before the standby mode command is sent, it is strongly recommended to read key data frst. lcd display on/off name command option description def. d7 d6 d5 d4 d3 d2 d1 d0 system set 1 0 0 0 0 0 d s s standby mode selecting {0}: standby mode {1}: normal mode 80h d lcd display on/off {0}: lcd display off {1}: lcd display on mode set command this command is used to set the follow function s . display mode selecting, 20*4 display mode or 16*8 display mode. set the HT16K23 seg/int port to be a segment output or an int output. int output is active-low or active-high. name command option description def. d7 d6 d5 d4 d3 d2 d1 d0 mode set 1 0 1 0 0 act int/ row m m lcd display mode selecting {0}: 20*4 display mode {1}:16*8 display mode a0h int/ row segment or int pin selecting {0}: segment output seg19/com4/k19/int is segment output in 20*4 display mode. seg15/k15/int is segment output in 16*8 display mode. {1}: int output seg19/com4/k19/int is int output in 20*4 display mode. seg15/k15/int is int output in 16*8 display mode. act int output level selection, {0}: int output is active-low. {1}: int output is active-high. system oscillator the internal logic and the lcd driver signals of the HT16K23 are timed by the integrated rc oscillator. the system clock frequency (f sys ) determines the lcd frame frequency. a clock signal must always be supplied to the device as removing the clock may freeze the standby mode command is executed. at initial system power on, the system oscillator is in the stop state.
rev. 1.10 11 july 01, 2011 HT16K23 lcd bias generator the full-scale lcd voltage (vop) is obtained from v dd C v ss . fractional lcd biasing voltages are obtained from an internal voltage divider of three series resistors connected between v lcd and v ss . the centre resistor can be switched out of the circuit to provide a 1/3 bias voltage level for the 1/4 duty confguration or 1/4 bias voltage level for the 1/8 duty confguration. segment driver outputs the lcd driver section includes segment outputs which should be connected directly to the lcd panel. the segment output signals are generated in accordance with the multiplexed column signals and with the data resident in the display latch. the unused segment outputs should be left open-circuit. common driver outputs the lcd driver section includes column outputs which should be connected directly to the lcd panel. the common output signals are generated in accordance with the selected lcd drive mode. the unused column outputs should be left open-circuit. display memory C ram structure the display ram is a static 16 x 8-bit ram where the lcd data is stored. a logic 1 in the ram bit-map indicates the on state of the corresponding lcd segment; similarly a logic 0 indicates the of f state. there is a one-to-one correspondence between the ram addresses and the segment outputs, and between the individual bits of a ram word and the column outputs. the following tables show the mapping from the ram to the lcd pattern: output com3 com2 com1 com0 output com3 com2 com1 com0 address seg1 seg0 00h seg3 seg2 01h seg5 seg4 02h seg7 seg6 03h seg9 seg8 04h seg11 seg10 05h seg13 seg12 06h seg15 seg14 07h seg17 seg16 08h seg19 seg18 09h d7 d6 d5 d4 d3 d2 d1 d0 data ram mapping of 20*4 display mode
rev. 1.10 12 july 01, 2011 HT16K23 output com7 com6 com5 com4 com3 com2 com1 com0 address seg0 00h seg1 01h seg2 02h seg3 03h seg4 04h seg5 05h seg6 06h seg7 07h seg8 08h seg9 09h seg10 0ah seg11 0bh seg12 0ch seg13 0dh seg14 0eh seg15 0fh d7 d6 d5 d4 d3 d2 d1 d0 data ram mapping of 16*8 display mode d 7 d 6 d 5 d 4 d3 d2 d1 d0 msb lsb
rev. 1.10 13 july 01, 2011 HT16K23 lcd drive mode waveforms 20*4 display mode, 1/4 duty , 1/3 bias v dd v1 v2 v ss com0 v dd v1 v2 v ss com1 v dd v1 v2 v ss com2 v dd v1 v2 v ss com3 v dd v1 v2 v ss seg0/k0~ seg19/k19 1 frame key scan period display period
rev. 1.10 14 july 01, 2011 HT16K23 16*8 display mode, 1/8 duty , 1/4 bias v dd v1 v2 v3 v ss com0 v dd v1 v2 v3 v ss com1 v dd v1 v2 v3 v ss com2 v dd v1 v2 v3 v ss com3 v dd v1 v2 v3 v ss com4 v dd v1 v2 v3 v ss com5 v1 v dd v2 v3 v ss com6 v1 v dd v2 v3 v ss com7 v1 v dd v2 v3 v ss seg0/k0~ seg16/k16 display period key scan period 1 frame
rev. 1.10 15 july 01, 2011 HT16K23 keyscan the HT16K23 supports a 20*1 matrix key scan in the 20*4 display mode and a 16*1 matrix key scan in the 16*8 display mode. the h ardware interrupt function is optional, allowing seg19/com4/k19/int in the 20*4 display mode or seg15/k15/int to be used as an int output or as a segment driver. the interrupt fag can be read (polled) through the serial interface instead . the key scan input pins are shared with segment output pins. the keyscan cycle loops continuously with time, with all keys experiencing a full keyscan debounce of over 20ms. a key press is debounced and an interrupt issued if at least one key that was not pressed in a previous cycle is found pressed during both sampling periods. int output is active-low when the act bit of the mode set command is set to 0, int output is active-high when the act bit of the mode set command is set to 1 keyscan and int timing the key data is updated and the int function is changed if the key has been pressed for 2 key-cycles. the int function is changed when the frst key has been pressed. after the key data has been read, the key data registers are cleared to 0 and the int fag bit is set to 0. the int pin goes low when the act bit of the mode set command is set to 1. after the key data has been read, the key data registers are cleared to 0 and the int fag bit is set to 1, and the int pin goes low when the act bit of the mode set command is set to 0. the int fag register is shown below. to clear the int fag status, the key data register must be read from 0x20h~0x22h in one operation. int fag register address code r/w register data d7 d6 d5 d4 d3 d2 d1 d0 def. int fag register 0x30h r 0 0 0 0 0 0 0 int fag 00h 1st frame 2nd frame 3rd frame 4th frame 5th frame 6th frame int flag int pin(active high) int pin(active low) when the interrupt asserted if required : 1. key data are updated 2. slave address are updated when after the all key data has been read: 1. clears the key debounced register. 2. the int flag bit is set to"0 3.the int pin goes to low when "act bit is set to 1. 4.the int pin goes to high when "act bit is ise to 0. press first key 7th frame 8th frame realease key 9th frame key data updated realease key press second key
rev. 1.10 16 july 01, 2011 HT16K23 key matrix confguration there is a key scan circuit integral to the HT16K23 which can detect a key press. it includes twenty inputs (k0 to k19, shared with seg0 to seg19) in the 20*4 display mode or sixteen inputs (k0 to k15, shared with seg0 to seg15) in the 16*8 display mode. the key matrix has a 20*1 matrix in the 20*4 display mode or a 16*1 matrix in the 16*8 display confguration as shown below: s e g 0/ k 0 s e g 1/ k 1 s e g 2/ k 2 s e g 3/ k 3 s e g 4/ k 4 s e g 5/ k 5 s e g 6/ k 6 s e g 7 /k 7 s e g 8/ k 8 s e g 9/k 9 s e g 10 /k 10 s e g 11 /k 11 s e g 12 /k 12 s e g 13 /k 13 s e g 14 /k 14 s e g 15 /k 15 s e g 16 /k 16 s e g 17 /k 17 s e g 18 /k 18 s e g 19 /k 19 vdd = vdd s e g 0/k 0 s e g 1/k 1 s e g 2/k 2 s e g 3/k 3 s e g 4/k 4 s e g 5/k 5 s e g 6/k 6 s e g 7 /k 7 s e g 8/k 8 s e g 9/k 9 s e g 10 /k 10 s e g 11 /k 11 s e g 12 /k 12 = s e g 13 /k 13 s e g 14 /k 14 s e g 15 /k 15 20*1 matrix in 20*4 display mode 16*1 matrix in 16*8 display mode key data register after the key data registers have been read, the key data registers are cleared to 0. to enable future key presses to be identifed, if the key data register is not read, the key data accumulates. there is no fifo register in the HT16K23. key-press order, or whether a key has been pressed more than once, cannot be determined unless the all of the key data ram is read after each interrupt and before completion of the next keyscan cycle. after the key data registers have been read, the int output and int fag status are cleared. if a key is pressed and held down, the key is reported as being debounced (and an int is issued) only once. the key must be detected as released by the keyscan circuit before it is debounced again. it is strongly recommended to read the key data registers from the address 0x20h only. the key data registers of addresses from 0x20h to 0x22h should be read continuously and completed in one operation. there is a one-to-one correspondence between the key data register addresses and the key data outputs and between the individual bits of a key data register word and the key data outputs. the following shows the mapping from the ram to the key data output: the key data registers are read only. the key data register format is shown below: key data register address code r/w register data d7 d6 d5 d4 d3 d2 d1 d0 def. key data register address point 0x20h r k7 k6 k5 k4 k3 k2 k1 k0 00h 0x21h r k15 k14 k13 k12 k11 k10 k9 k8 00h 0x22h r 0 0 0 0 k19 k18 k17 k16 00h
rev. 1.10 17 july 01, 2011 HT16K23 key scan period setting command HT16K23 can adjust the key scan period through this command. the setting is show as below. the default value of key scan period is 2 clock cycle time in 20*4 display mode, 1 clock cycle time in 16*8 display mode. in generally, user does not need to use this command, when key data can be read correctly. due to various lcd characteristic, it will have different rc time constant in key scan period. if the equivalent capacitance is larger in the lcd, it can not be charged or discharged fully in key scan period. the key can not be read correctly. to avoid read key error, user can adjust the key scan period through this command. if key scan period is too longer, it may affect the lcd visual quality. name command option description def. d7 d6 d5 d4 d3 d2 d1 d0 key scan period setting 1 1 1 1 1 p2 p1 p0 [p2:p0] to adjust key scan period f8h t he setting of key scan period [p2:p0] 20*4 display mode 16*8 display mode 000 2 clock cycle time 1 clock cycle time 001 4 clock cycle time 3 clock cycle time 010 6 clock cycle time 5 clock cycle time 011 8 clock cycle time 7 clock cycle time 100 10 clock cycle time 9 clock cycle time 101 12 clock cycle time 11 clock cycle time 110 14 clock cycle time 13 clock cycle time 111 16 clock cycle time 15 clock cycle time the relationship of display period and key scan period v dd v1 v2 v ss com0~ com3 v dd v1 v2 v ss seg0/k0~ seg19/k19 key scan period display period t v1 v dd v2 v3 v ss com0~ com7 v1 v dd v2 v3 v ss seg0/k0~ seg16/k16 key scan period display period t 20*4 display mode t= display period + key scan period = 110 clock cycle time (fxed) t= display period + key scan period = 55 clock cycle time (fxed) 16*8 display mode
rev. 1.10 18 july 01, 2011 HT16K23 i 2 c serial interface the device includes a i 2 c serial interface. the i 2 c bus is used for bidirectional, two-line communication between different ics or modules. the two lines are a serial data line (sda) and a serial clock line (scl). both lines are connected to a positive supply via a pull-up resistor. when the bus is free, both lines are high. the output stages of devices connected to the bus must have an open-drain or open-collector output type to implement the required wired and function. data transfer is initiated only when the bus is not busy. data validity the data on the sda line must be stable during the high period of the clock. the high or low state of the data line can only change when the clock signal on the scl line is low (see as below). sda scl data line stable, data valid chang of data allowed start and stop conditions a high to low transition on the sda line while scl is high defnes a start condition. a low to high transition on the sda line while scl is high defnes a stop condition. start and stop conditions are always generated by the master. the bus is considered to be busy after the start condition. the bus is considered to be free again a certain time after the stop condition. the bus stays busy if a repeated start (sr) is generated instead of a stop condition. in this respect, the start(s) and repeated start (sr) conditions are functionally identical. p s sda scl sda scl start condition stop condition byte format every byte put on the sda line must be 8-bits long. the number of bytes that can be transmitted per transfer is unrestricted. each byte has to be followed by an acknowledge bit. data is transferred with the most signifcant bit (msb) frst. s or sr p or sr sda scl 1 2 7 8 9 ack 1 2 3 - 8 9 ack p sr
rev. 1.10 19 july 01, 2011 HT16K23 acknowledge each byte of eight bits is followed by a single acknowledge bit. this acknowledge bit is a low level which is placed on the bus by the receiver . t he master generates an extra acknowledge related clock pulse. a slave receiver which is addressed must generate an acknowledge (ack) after the reception of each byte. the acknowledg ing device must pull down the sda line during the acknowledge clock pulse so that it remains at a stable low level during the high period of this clock pulse. a master receiver must signal an end of data status to the slave by generating a not-acknowledge (nack) bit on the last byte that has been clocked out of the slave. in this case, the master receiver must leave the data line high during the 9th pulse to not acknowledge. the master will generate a stop or repeated start condition. s 1 2 7 8 9 clk pulse for acknowledgement data output by transmiter data output by receiver scl from master acknowledge not acknowledge start condition device addressing the slave address byte is the frst byte received following a start condition form the master device. the frst seven bits of the frst byte make up the slave address. the eighth bit defnes whether a read or write operation is to be performed. when this r/ w bit is 1, then a read operation is selected. a 0 selects a write operation. the HT16K23 address bit format is shown below. when an address byte is sent, the device compares the frst seven bits after the start condition. if they match, the device outputs an acknowledge on the sda line. 1 1 1 0 0 1 1 r/w msb lsb device address
rev. 1.10 20 july 01, 2011 HT16K23 write operation byte write operation a byte write operation requires a start condition, a slave address with an r/ w bit, a valid register address, data and a stop condition. after each of the three bytes have been transmitted, the device responds with an ack. 1 1 1 0 0 1 1 0 s ack p slave address write command code ack command byte received 1 1 1 0 0 1 1 0 s ack p slave address write register address(an) data(n) ack ack single data byte received note: if the byte following slave address is a command code, the byte following the command code will be ignored. page write operation a start condition and a slave address with a r/ w bit placed on the bus indicates to the addressed device that a register address will follow and is to be written to the address pointer. the data to be written to the memory is next and the internal address pointer will be incremented to the next address location on the reception of an acknowledge clock. after reaching the memory location 0x8ah in the 20*4 display mode or 0x8fh in the 16*8 display mode, the pointer will be reset to 0x80h. 1 1 1 0 0 1 1 0 s ack slave address write register address(an) data(n) ack ack ack data(n+1) ack ack data(n+x) p n data bytes received
rev. 1.10 21 july 01, 2011 HT16K23 read operation in this mode, the master reads the HT16K23 data after setting the slave address. following a r/ w bit (=0) and an acknowledge bit, the register address (an) is written to the address pointer. next a start condition and a slave address are repeated followed by a r/ w bit (=1). the data which was addressed is then transmitted. the address pointer is only incremented on reception of an acknowledge clock. the HT16K23 will place the data at address an+1 on the bus. the master reads and acknowledges the new byte and the address pointer is incremented to an+2. if the register address (an) is 0x00h ~ 0x0fh, after reaching the memory location 0x0fh, the pointer will reset to 0x00h. if the register address (an) is 0x20h ~ 0x22h, after reaching the memory location 0x22h, the pointer will reset to 0x20h. this cycle of reading consecutive addresses will continue until the master sends a stop condition. 1 1 1 0 0 1 1 1 s slave address read data(n) ack ack ack data(n+1) ack data(n+x) p 1 1 1 0 0 1 1 0 s ack slave address write register address(an) p ack nack
rev. 1.10 22 july 01, 2011 HT16K23 command summary name command / address option description def. d7 d6 d5 d4 d3 d2 d1 d0 display data address pointer 0 0 0 0 a3 a2 a1 a0 [a3:a0] (r/w) four bits of immediate data, bits a0 to a4, are transferred to the data pointer to defne display ram addresses. 00h key data address pointer 0 0 1 0 0 0 k1 k0 {k0~k1} (r) it is strongly recommended that the key data registers with addresses from 0x20h to 0x22h should be read continuously and in one operation. therefore the key data ram addresses should be started form 0x20h only. 20h int fag address pointer 0 0 1 1 0 0 0 0 (r) int fag address for reading int fag status. 30h system set command 1 0 0 0 0 0 d s s standby mode selecting {0}: standby mode {1}: normal mode 80h d lcd display on/off {0}: lcd display off {1}: lcd display on mode set command 1 0 1 0 0 act int/ row m m lcd display mode selecting {0}: 20*4 display mode {1}:16*8 display mode a0h int/row segment or int pin selecting {0}: segment output seg19/com4/k19/int is segment output in 20*4 display mode. seg15/k15/int is segment output in 16*8 display mode. {1}: int output seg19/com4/k19/int is int output in 20*4 display mode. seg15/k15/int is int output in 16*8 display mode. act int output level selection, {0}: int output is active-low. {1}: int output is active-high. key scan period setting 1 1 1 1 1 p2 p1 p0 [p2:p0] to adjust key scan period f8h note: if the programmed command data is not defned, the function will not be af fected.
rev. 1.10 23 july 01, 2011 HT16K23 HT16K23 operation flow chart the a ccess procedure is illustrated using the following fowcharts. initiali s ation power on mode set system set display on power on display data rewrite C address setting start next processing display data display data ram write address setting
rev. 1.10 24 july 01, 2011 HT16K23 key data read no yes start int flag bit =1 ? read key data next processing port configuration register set int / row bit=1? yes no clear int flag no yes int pin bit =1 ? read key data next processing int pin is set to low level no yes int pin bit =0 ? read key data next processing int pin is set to high level act bit is set to 0=? yes no
rev. 1.10 25 july 01, 2011 HT16K23 application circuit 20*4 display mode without int lcd panel scl sda vdd vss mcu vdd vss HT16K23 vss r 0.1uf seg11/k11 seg12/k12 seg13/k13 seg14/k14 seg15/k15/int seg16/com7/k16 seg17/com6/k17 seg18/com5/k18 com3 com2 com1 com0 vdd seg4/k4 seg5/k5 seg6/k6 seg7/k7 seg8/k8 seg9/k9 seg10/k10 r seg3/k3 seg2/k2 seg1/k1 seg0/k0 seg19/com4/k19/int vdd r1x20 = 4.7k 4.7k 19*4 display mode with int lcd panel scl sda vdd vss mcu vdd vss HT16K23 vss r 0.1uf seg11/k11 seg12/k12 seg13/k13 seg14/k14 seg15/k15/int seg16/com7/k16 seg17/com6/k17 seg18/com5/k18 com3 com2 com1 com0 vdd seg4/k4 seg5/k5 seg6/k6 seg7/k7 seg8/k8 seg9/k9 seg10/k10 r seg3/k3 seg2/k2 seg1/k1 seg0/k0 seg19/com4/k19/int = vdd r1x19 4.7k 4.7k note: r1=180k ~ 220k, adjust r1 to ft the lcd visual quality.
rev. 1.10 26 july 01, 2011 HT16K23 16*8 display mode without int lcd panel scl sda vdd vss mcu vdd vss HT16K23 vss r 0.1uf seg11/k11 seg12/k12 seg13/k13 seg14/k14 seg15/k15/int com3 com2 com1 com0 vdd seg4/k4 seg5/k5 seg6/k6 seg7/k7 seg8/k8 seg9/k9 seg10/k10 r seg3/k3 seg2/k2 seg1/k1 seg0/k0 seg16/com7/k16 seg17/com6/k17 seg18/com5/k18 seg19/com4/k19/int = vdd r1x16 4.7k 4.7k 15*8 display mode with int lcd panel scl sda vdd vss mcu vdd vss HT16K23 vss r 0.1uf seg11/k11 seg12/k12 seg13/k13 seg14/k14 seg15/k15/int com3 com2 com1 com0 vdd seg4/k4 seg5/k5 seg6/k6 seg7/k7 seg8/k8 seg9/k9 seg10/k10 r seg3/k3 seg2/k2 seg1/k1 seg0/k0 seg16/com7/k16 seg17/com6/k17 seg18/com5/k18 seg19/com4/k19/int = vdd r1x15 4.7k 4.7k note: r1=180k ~ 220k, adjust r1 to ft the lcd visual quality.
rev. 1.10 27 july 01, 2011 HT16K23 package information 28-pin sop (300mil) outline dimensions ms-013 symbol dimensions in inch min. nom. max. a 0.393 D 0.419 b 0.256 D 0.300 c 0.012 D 0.020 c 0.697 D 0.713 d D D 0.104 e D 0.050 D f 0.004 D 0.012 g 0.016 D 0.050 h 0.008 D 0.013 0 D 8 symbol dimensions in mm min. nom. max. a 9.98 D 10.64 b 6.50 D 7.62 c 0.30 D 0.51 c 17.70 D 18.11 d D D 2.64 e D 1.27 D f 0.10 D 0.30 g 0.41 D 1.27 h 0.20 D 0.33 0 D 8
rev. 1.10 28 july 01, 2011 HT16K23 reel dimensions product tape and reel specifications reel dimensions sop 28w (300mil) symbol description dimensions in mm a reel outer diameter 330.01.0 b reel inner diameter 100.01.5 c spindle hole diameter 13.0 +0.5/-0.2 d key slit width 2.00.5 t1 space between flange 24.8 +0.3/-0.2 t2 reel thickness 30.20.2 package information 2 april 1, 2010 sop 28w (300mil) symbol description dimensions in mm a reel outer diameter 330.01.0 b reel inner diameter 100.01.5 c spindle hole diameter 13.0 +0.5/-0.2 d key slit width 2.00.5 t1 space between flange 24.8 +0.3/-0.2 t2 reel thickness 30.20.2
rev. 1.10 29 july 01, 2011 HT16K23 carrier tape dimensions carrier tape dimensions sop 28w (300mil) symbol description dimensions in mm w carrier tape width 24.00.3 p cavity pitch 12.00.1 e perforation position 1.750.10 f cavity to perforation (width direction) 11.50.1 d perforation diameter 1.5 +0.1/-0.0 d1 cavity hole diameter 1.50 +0.25/-0.00 p0 perforation pitch 4.00.1 p1 cavity to perforation (length direction) 2.00.1 a0 cavity length 10.850.10 b0 cavity width 18.340.10 k0 cavity depth 2.970.10 t carrier tape thickness 0.350.01 c cover tape width 21.30.1 package information 3 april 1, 2010

sop 28w (300mil) symbol description dimensions in mm w carrier tape width 24.00.3 p cavity pitch 12.00.1 e perforation position 1.750.10 f cavity to perforation (width direction) 11.50.1 d perforation diameter 1.5 +0.1/-0.0 d1 cavity hole diameter 1.50 +0.25/-0.00 p0 perforation pitch 4.00.1 p1 cavity to perforation (length direction) 2.00.1 a0 cavity length 10.850.10 b0 cavity width 18.340.10 k0 cavity depth 2.970.10 t carrier tape thickness 0.350.01 c cover tape width 21.30.1
rev. 1.10 30 july 01, 2011 HT16K23 holtek semiconductor inc. (headquarters) no.3, creation rd. ii, science park, hsinchu, taiwan tel: 886-3-563-1999 fax: 886-3-563-1189 http://www.holtek.com.tw holtek semiconductor inc. (taipei sales offce) 4f-2, no. 3-2, yuanqu st., nankang software park, taipei 115, taiwan tel: 886-2-2655-7070 fax: 886-2-2655-7373 fax: 886-2-2655-7383 (international sales hotline) holtek semiconductor inc. (shenzhen sales offce) 5f, unit a, productivity building, no.5 gaoxin m 2nd road, nanshan district, shenzhen, china 518057 tel: 86-755-8616-9908, 86-755-8616-9308 fax: 86-755-8616-9722 holtek semiconductor (usa), inc. (north america sales offce) 46729 fremont blvd., fremont, ca 94538, usa tel: 1-510-252-9880 fax: 1-510-252-9885 http://www.holtek.com copyright ? 2011 by holtek semiconductor inc. the information appearing in this data sheet is believed to be accurate at the time of publication. however, holtek assumes no responsibility arising from the use of the specifications described. the applications mentioned herein are used solely for the purpose of illustration and holtek makes no warranty or representation that such applications will be suitable without further modifcation, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. holtek's products are not authorized for use as critical components in life support devices or systems. holtek reserves the right to alter its products without prior notifcation. for the most up-to-date information, please visit our web site at http://www.holtek.com.tw .

▲Up To Search▲

Price & Availability of HT16K23

	To Download HT16K23 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .